Electronic devices need electrical energy to operate. In a portable electronic device, a battery is typically provided, and electrical energy is drawn from the battery to power integrated circuits comprised in the electronic device. Moreover, a number of driving factors that are continuously improving the system level performance including but not limited to smaller form-factor with higher data transfer rate, signal integrity, memory bandwidth, power and thermal management capability etc. It is of highest importance that the today's integrated and portable products are continuously striving to improve at least those metrics. The maturity of the Through Silicon Via (TSV) technology has opened up enormous possibilities for homogenous and heterogeneous integration of logic, analog, sensors and memory co-located closely together in a small form-factor assembly. Moreover, TSV technology breakthrough and maturity has enabled exploiting the possibilities of advancing the interposer packaging technology to the next level. Some good examples of interposers including TSV are disclosed in U.S. Pat. Nos. 8,426,961 B2, 8,928,132B2, 8,426,961 B2, 8,263,434B2. Adaptation of interposer technology is steadily increasing in the semiconductor industry. Interposer technology brings multiples of benefits including enabling heterogeneous die packaging, shorter interconnect lines by means of TSVs, integrated passive devices (IPD), vertical package integration etc. Such integration enables to gain high density I/O so that different types of dies can be located near to each other on a TSV interposer e.g. logic and memory. Such technology is also known as 2.5D packaging technology. Moreover, silicon dies can be stacked tier-to-tier on top of each other, which reduces the physical area for defined components. Such tier-to-tier stacking is called 3D packaging technology.
However, integration of such densely populated dies may come with a price. Many low-power, high speed integrated circuits are extremely sensitive to electrical noise generated by the continuous switching of the transistors located in the circuit blocks. A known solution to this problem is to connect the circuit with a so called decoupling capacitor to minimize the power fluctuation induced noise. A decoupling capacitor essentially stores charge locally, which can then give out required energy to compensate for any sudden fluctuations or voltage variations during transistor switching stages and thereby minimize any voltage noise so that the circuit can continue functioning smoothly, and thereby enhanced performance is achieved.
It is also known that the impact of the inductance becomes more crucial as the frequency of the circuit goes up. Hence, an important improvement is to have such decoupling capacitor as close as possible to the intended circuit, for which it should serve to reduce the parasitic inductance coming from the interconnect lines. Many approaches have been made to produce integrated decoupling capacitor, e.g. exploiting part of gate dielectric layer, exploiting the spaces between the metal layers of the circuit, multi-layer dissimilar materials stacked capacitor structures, etc. Such approaches however suffer from either the need for a substantial footprint of active silicon area, dielectric leakage, parasitic resistance, or are limited by the fundamental limitations in increasing in capacitance per unit area defined by the parallel plate area or from processing complexity or cost. A good example of different approaches is disclosed in the U.S. Pat. 7,416,954B2.
Advantages of having an integrated silicon based capacitor on an interposer are explained in the U.S. Pat. No. 7,518,881B2. Such integration enables to reduce voltage noise on an integrated (IC) circuit device that may be connected to the capacitor integrated interposer. The main advancement of the disclosure was that the capacitor was brought closer to the IC by having it integrated at the surface of the interposer where the IC will be connected. A variation of such an approach is disclosed in U.S. Pat. No. 7,488,624B2 where it is described how to configure multiples of silicon based integrated capacitors in an interposer. Yet another example of an integrated capacitor is disclosed in U.S. Pat. No. 8,618,651B1, where silicon capacitors are formed within blind TSV vias. Another example of silicon trench based capacitor is disclosed in U.S. Pat. No. 9,236,442B2, where high aspect ratio silicon trenches are used to manufacture capacitor devices. A variation of a trench capacitor manufacturing method is disclosed in U.S. Pat. No. 9,257,383B2.
Hence, traditional silicon based embedded high aspect ratio trench capacitor technology has matured to be used for volume production and may be found in today's smartphone packaging. However, given the trend in miniaturization, the potential of the silicon based capacitor technology is limited by the ability to tailor the capacitor density per unit area, undesired parasitic resistances, increased film stress in the silicon substrate during processing, escalated manufacturing complexity and economy of costs per functions.
A typical interposer may be made of a thin slab of bulk semiconductor material e.g. Silicon which may require TSVs as interconnects. The TSV vias may induce reliability challenges due to non-optimal stress distribution from the vias and the mismatch of the coefficient of thermal expansion (CTE) between the bonded substrate and the interposer as disclosed in U.S. Pat. No. 9,349,669 B2. Additionally, the basic trench based capacitor technology for example MIM capacitor can induce significant tensile stress on the silicon with high trench densities and hence can cause a silicon wafer to warp or bow upwards as disclosed in U.S. Pat. No. 8,963,287 B1.
Furthermore, for many integrated circuits, it would be desirable to also store energy locally. However, local energy storage in an integrated circuit requires the use of valuable space and/or processing that either may not be compatible with standard so called front end manufacturing processes or may not be economically advantageous or combination thereof.
Additionally, for many cases for packaging of integrated circuits into a system such as SoC or SiP packaging, it would be desirable to be able to control the thickness of the interposer devices without increasing the processing complexity and/or processing cost. Hence, there are apparently a number of avenues where the interposer assembly technology can further be improved and the present described invention disclosures intends to contribute to enable a smarter, better and cost effective interposer with reduced film stress, better control over the interposer thickness and added functionality to be used as an assembly platform.